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HD74CDCV857
2.5-V Phase-lock Loop Clock Driver
REJ03D0135-0700Z (Previous ADE-205-335E (Z)) Preliminary Rev.7.00 Oct.09.2003
Description
The HD74CDCV857 is a high-performance, low-skew, low-jitter, phase locked loop clock driver. It is specifically designed for use with DDR (Double Data Rate) synchronous DRAMs.
Features
* * * * * * * * * DDR266 / PC2100-Compliant Supports 60 MHz to 170 MHz operation range Distributes one differential clock input pair to ten differential clock outputs pairs Supports spread spectrum clock requirements meeting the PC100 SDRAM registered DIMM specification External feedback pins (FBIN, FBIN) are used to synchronize the outputs to the clock input Supports 2.5V analog supply voltage (AVCC), and 2.5 V VDDQ No external RC network required Sleep mode detection 48pin TSSOP (Thin Shrink Small Outline Package)
Function Table
Inputs AVCC GND GND X X 2.5 V 2.5 V 2.5 V H: L: X: Z: Note: PWRDWN CLK H H L L H H X L H L H L H CLK H L H L H L : : : : : : : : : Outputs Y L H Z Z H H Z Y H L Z Z L L Z FBOUT L H Z Z H H Z FBOUT : H L Z Z L L Z : : : : : : : PLL Bypassed / off *1 Bypassed / off *1 off off on on off
0 MHz 0 MHz
High level Low level Don't care High impedance 1. Bypasse mode is used for RENESAS test mode.
Rev.7.00, Oct.09.2003, page 1 of 12
HD74CDCV857
Pin Arrangement
GND 1 Y0 2 Y0 3 V DDQ 4 Y1 5 Y1 6 GND 7 GND 8 Y2 9 Y2 10 V DDQ 11 V DDQ 12 CLK 13 CLK 14 V DDQ 15 AV CC 16 AGND 17 GND 18 Y3 19 Y3 20 V DDQ 21 Y4 22 Y4 23 GND 24
48 GND 47 Y5 46 Y5 45 V DDQ 44 Y6 43 Y6 42 GND 41 GND 40 Y7 39 Y7 38 V DDQ 37 PWRDWN 36 FBIN 35 FBIN 34 V DDQ 33 FBOUT 32 FBOUT 31 GND 30 Y8 29 Y8 28 V DDQ 27 Y9 26 Y9 25 GND
(Top view)
Rev.7.00, Oct.09.2003, page 2 of 12
HD74CDCV857
Pin Function
Pin name AGND AVCC No. 17 16 Type Ground Power Description Analog ground. AGND provides the ground reference for the analog circuitry. Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. This bypass mode is used for RENESAS test. Clock input. CLK provides the clock signal to be distributed by the HD74CDCV857 clock driver. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal. Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN. Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. Output bank enable. PWRDWN is the output enable for all outputs. When PWRDWN is low, VCO will stop and all outputs are disabled to a high impedance state. When PWRDWN will be returned high, PLL will re-synchroniz to CLK frequency and all outputs are enabled. Ground
CLK, CLK
13, 14
I
Differential input
FBIN, FBIN
35, 36
I
Differential input
FBOUT, FBOUT 32, 33
O
Differential output
PWRDWN
37
I
GND
1, 7, 8, 18, 24, 25, 31, 41, 42, 48 4, 11, 12, 15, 21, 28, 34, 38, 45
Ground
VDDQ
Power
Power supply
Y
3, 5, 10, 20, O 22, 27, 29, Differential output 39, 44, 46 2, 6, 9, 19, 23, 26, 30, 40, 43, 47 O
Differential output
Clock outputs. These outputs provide low-skew copies of CLK.
Y
Clock outputs. These outputs provide low-skew copies of CLK.
Rev.7.00, Oct.09.2003, page 3 of 12
HD74CDCV857
Logic Diagram
PWRDWN AVCC
37
3 2
Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 Y9 Y9 FBOUT FBOUT
16
Powerdown and Test Logic
5 6 10 9 20 19 22 23 46 47 44 43 39 40
CLK CLK FBIN FBIN
13 14
29 30
PLL
36 35
27 26 32 33
Note: All inputs and outputs are associated with VDDQ = 2.5 V.
Rev.7.00, Oct.09.2003, page 4 of 12
HD74CDCV857
Absolute Maximum Ratings
Item Supply voltage Input voltage Output voltage *1 Input clamp current Output clamp current Continuous output current Maximum power dissipation at Ta = 55C (in still air) Storage temperature Notes: Tstg Symbol VDDQ, ACC VI VO IIK IOK IO Ratings -0.5 to 3.6 -0.5 to VDDQ+0.5 -0.5 to VDDQ +0.5 -50 -50 50 100 0.7 -65 to +150 Unit V V V mA mA mA mA W C VI < 0 VO < 0 VO = 0 to VDDQ Conditions
Supply current through each VDDQ or GND IVDDQ or IGND
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
Rev.7.00, Oct.09.2003, page 5 of 12
HD74CDCV857
Recommended Operating Conditions
Item Supply voltage Output supply voltage DC input signal voltage High level input voltage Low level input voltage Differential input signal voltage Differential cross point voltage *2 Output current Input slew rate Operating temperature Notes:
*1
Symbol AVCC VDDQ VIHG VILG VID VIX VOX *3 IOH IOL SR Ta
Min 2.3 2.3 -0.3 1.7 -0.3 0.36 0.5xVDDQ -0.20 -- -- 1 0
Typ 2.5 2.5 -- -- -- -- -- -- -- -- --
Max 2.7 2.7
Unit Conditions V V All pins PWRDWN input pin PWRDWN input pin
VDDQ+0.3 V VDDQ+0.3 V 0.7 0.5xVDDQ +0.20 -12 12 4 70 V V mA VDDQ+0.6 V
V/ns 20% - 80% C
Inputs pins must be prevent from floating. Feedback inputs (FBIN, FBIN) may float when the device is in low power mode. 1. DC input signal voltage specifies the allowable dc execution of differential input. 2. Differential cross point voltage is expected to track variations of VDDQ and is the voltage at which the differential signals must be crossing. (See figure1) 3. Guaranteed by design, not 100% tested in production.
CLK VID CLK Crossing point
Figure 1 Differential input levels
Rev.7.00, Oct.09.2003, page 6 of 12
HD74CDCV857
Electrical Characteristics
Item Symbol Min -- VDDQ- 0.2 1.7 VOL Input current Input capacitance Delta input capacitance Supply current Supply current in power down mode Note: II CI CDI DICC AICC ICCpd -- -- -- 2.5 -0.25 -- -- -- Typ *1 -- -- -- -- -- -- -- -- 250 9 -- Max -1.2 -- -- 0.2 0.6 10 3.5 0.25 300 12 100 A A pF pF mA Unit V V Test Conditions II = -18 mA, VDDQ = 2.3 V IOH = -100 A, VDDQ = 2.3 to 2.7 V IOH = -12 mA, VDDQ = 2.3 V IOL = 100 A, VDDQ = 2.3 to 2.7 V IOL = 12 mA, VDDQ = 2.3 V VI = 0 V to 2.7 V, VDDQ = 2.7 V CLK and CLK, FBIN and FBIN CLK and CLK, FBIN and FBIN
f = 170 MHz, VDDQ = AVCC = 2.7 V, All Yx, Yx pin = open
Input clamp CLK, CLK VIK voltage FBIN, FBIN, G Output voltage VOH
1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
Rev.7.00, Oct.09.2003, page 7 of 12
HD74CDCV857
Switching Characteristics
Item Period jitter Half period jitter Cycle to cycle jitter Static phase offset Output clock skew Application clock frequency Slew rate PLL stabilization time Symbol tPER tHPER tCC tSPE tsk fCLK(A) tSL tSTAB Min -75 -100 -75 -75 -- 60 95 1.0 -- Typ -- -- -- -- -- -- 133 -- -- Max 75 100 75 75 100 200 170 2.0 0.1 Unit Test Conditions Notes ps ps ps ps ps See figure 6, 9 See figure 7, 9 See figure 5, 9 See figure 3, 9 See figure 4, 9 1, 2 1, 3 20% - 80% 6, 10 7, 8 8, 10 10 4, 5, 9, 10
Operating clock frequency fCLK(O)
MHz See figure 9 MHz See figure 9 V/ns See figure 9 ms See figure 9
Notes: 1. The PLL must be able to handle spread spectrum induced skew (the specification for this frequency modulation can be found in the latest Intel PC100 Registered DIMM specification) 2. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters. 3. Application clock frequency indicates a range over which the PLL must meet all timing parameters. 4 Assumes equal wire length and loading on the clock output and feedback path. 5. Static phase offset does not include jitter. 6. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up. 7. Period jitter defines the largest variation in clock period, around anominal clock period. 8. Period jitter and half period jitter are independent from each other. 9. Conditions at VDDQ = 2.5 V, Ta = 25C. 10. Guaranteed by design, not 100% tested in production.
Rev.7.00, Oct.09.2003, page 8 of 12
HD74CDCV857 Differential clock outputs are directly terminated by a 120 resistor. Figure 2 is typical usage conditions of outputs load.
V DDQ Device under OUT test
V DDQ
RT = 120
C = 14 pF
OUT C = 14 pF
Figure 2 Differential signal using direct termination resistor
CLKIN CLKIN FBIN FBIN tSPE
Figure 3 Static phase offset
FBOUT FBOUT Yx Yx tsk
Yx Yx Yx' Yx' tsk
Figure 4 Output skew
Rev.7.00, Oct.09.2003, page 9 of 12
HD74CDCV857
Yx, FBOUT Yx, FBOUT
t cycle n
t cycle n+1
t cc = t cycle n - t cycle n+1
Figure 5 Cycle to cycle jitter
Yx, FBOUT Yx, FBOUT
t cycle n
Yx, FBOUT Yx, FBOUT 1 fo 1 fo
t PER = t cycle n -
Figure 6 Period jitter
Yx, FBOUT Yx, FBOUT
t half period n
t half period n+1
Yx, FBOUT Yx, FBOUT 1 fo 1 2*fo
t HPER = t half period n -
Figure 7 Half period jitter
Rev.7.00, Oct.09.2003, page 10 of 12
HD74CDCV857
Yx, FBOUT
Yx, FBOUT
t half cycle n
t half cycle n+1
t HCC = t half cycle n - t half cycle n+1
Figure 8 Half cycle to cycle jitter
V DDQ AVCC Device under OUT test
V DDQ /2 AVCC /2 Z = 60 RT = 10 C= 14 pF -VDDQ /2 C= 14 pF -VDDQ /2
Oscillo scope
Z = 50 RT = 50 Z = 50 RT = 50
OUT AGND GND
Z = 60 -VDDQ /2
RT = 10
V DDQ AVCC Device under OUT test
V DDQ AV CC Z = 60 RT = 120
C= 14 pF
OUT AGND GND
Z = 60
C= 14 pF
Figure 9 Output load test circuit
Rev.7.00, Oct.09.2003, page 11 of 12
HD74CDCV857
Package Dimensions
As of January, 2002
12.5 12.7 Max
Unit: mm
25
48
1
*0.19 0.05
0.50
24
0.08 M
8.10 0.20
0 - 8
6.10
1.0
0.65 Max
*0.15 0.05
0.10
0.10 0.05
1.20 Max
0.50 0.1
*Pd plating
Package Code JEDEC JEITA Mass (reference value)
TTP-48DBV -- -- 0.20 g
Rev.7.00, Oct.09.2003, page 12 of 12
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